`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:16:18 09/17/2010 
// Design Name: 
// Module Name:    variable_mux 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module mux_4 # ( parameter N = 16 ) (
    output [N-1:0] out0,
    output [N-1:0] out1,
    output [N-1:0] out2,
    output [N-1:0] out3,
    input [N-1:0] in,
    input [1:0] select
    );	
	
parameter data0 	= 2'b00;
parameter data1		= 2'b01;
parameter t_data0	= 2'b10;
parameter t_data1	= 2'b11;	

reg [N-1:0] out_reg0;
reg [N-1:0] out_reg1;
reg [N-1:0] out_reg2;
reg [N-1:0] out_reg3;

assign out0 = out_reg0;
assign out1 = out_reg1;
assign out2 = out_reg2;
assign out3 = out_reg3;
	
always@( select, in )
begin
	case( select )
		data0:
		begin
			out_reg0[N-1:0] <= in[N-1:0];
			out_reg1 <= 0;
			out_reg2 <= 0;
			out_reg3 <= 0;
		end
		data1:
		begin
			out_reg0 <= 0;
			out_reg1[N-1:0] <= in[N-1:0];
			out_reg2 <= 0;
			out_reg3 <= 0;
		end
		t_data0:
		begin
			out_reg0 <= 0;
			out_reg1 <= 0;
			out_reg2[N-1:0] <= in[N-1:0];
			out_reg3 <= 0;
		end
		t_data1:
		begin
			out_reg0 <= 0;
			out_reg1 <= 0;
			out_reg2 <= 0;
			out_reg3[N-1:0] <= in[N-1:0];
		end
	endcase
end
endmodule
